Motivation
   • Early prediction of design characteristics
        • Interconnect wirelength 
        •                                          Done
          Interconnect fanout
        • Clock frequency
        •                                         Ongoing
          Area, etc.
   • Enable early-stage design space exploration
        • Abstractions of physically achievable system 
          implementations
        • Models to drive efficient system-level optimizations
   • Existing models fail to capture the impact of (1) 
      architectural and (2) implementation parameters
        • Significant deviation against layout data
                          UCSD VLSI CAD Laboratory  - ISOCC, Nov. 23, 2009                   (2/12)
   Existing Models
 • Wirelength statistics
      • Christie et al. [2000]
            • Point-to-point wirelength distribution based on Rent’s rule
            • Extends Davis et al. wirelength distribution model
            • Significant deviation against layout data
 • Fanout statistics
      • Zarkesh-Ha et al. [2000]
            • Error in counting the number of m-terminal nets per gate
            • Significant deviation against layout data
 • Existing models fail to take into account combined impacts of 
     architectural and implementation parameters
  Question: What is the impact of considering architectural 
     parameters in early prediction of physical implementation?
                          UCSD VLSI CAD Laboratory  - ISOCC, Nov. 23, 2009                   (3/12)
   Implementation Flow and Tools
                           Router / DFT RTL           Architectural
                          (Netmaker / SPIRAL)         Parameters
                              Synthesis
                           (Design Compiler)
  Implementation
    Parameters                                         Wirelength and 
                             Place + Route             Fanout Models
                           (SOC Encounter)
                                                      Model Generation
                            Wiring Reports            (Multiple Adaptive 
                                                     Regression Splines)
  • Timing-driven synthesis, place and route flow
  • Consider both architectural and implementation parameters for 
     more complete modeling of design space
  • Rent parameter extraction through internal RentCon scripts
                          UCSD VLSI CAD Laboratory  - ISOCC, Nov. 23, 2009                   (4/12)
   Design of Experiments
  • Netmaker  generation of fully synthesizable router RTL code
  • SPIRAL  generation of fully synthesizable DFT RTL code
  • Libraries: TSMC (1) 130G, (2) 90G, and (3) 65GP
  • Tools: Netmaker (University of Cambridge), SPIRAL (CMU), 
     Synopsys Design Compiler and PrimeTime, Cadence SOC 
     Encounter, Salford MARS 3.0
  • Experimental axes:
      •  Technology nodes: {130nm, 90nm, 65nm}
      •  Clock frequency
      •  Aspect ratio
      •  Row utilization
      •  Architectural parameters: {fw, nvc, nport, lbuf} for routers and 
         {n, width, t, nfifo} for DFT cores
                          UCSD VLSI CAD Laboratory  - ISOCC, Nov. 23, 2009                   (5/12)
   Modeling Problem
                                                                             →
   • Accurately predict y given vector of parameters x
                                                     →
   • Difficulties: (1) which variables x to use, and (2) how different 
       variables combine to generate y
                                              →
                                y = f(x)+noise
   • Parametric regression: requires a functional form
   • Nonparametric regression: learns about the best model from 
       the data itself
       For our purpose, allows decoupling of underlying
           architecture / implementation from modeling effort
   • We use nonparametric regression to model interconnect 
       wirelength (WL) and fanout (FO)
                          UCSD VLSI CAD Laboratory  - ISOCC, Nov. 23, 2009                   (6/12)